6.828 Lecture 4 - Page tables

  • Every memory address a CPU sees is assumed to be virtual (assuming satp is set?)

  • Almost all architectures use 4kb as the page size

  • The fact that RISC-V physical addresses are 56 bits wide is arbitrary and simply just part of the design

  • PTE flags:

    • V: valid/invalid
    • R/W/X: read/write/execute
    • U: accessible from user space
    • G: ???
    • A: ???

  • The TLB is opaque and inaccessible to the OS; the only real reason it’s relevant is that the OS needs to invalidate portions of the TLB (or flush it entirely) when the page tables are updated/changed.

  • On a TLB cache miss, is the CPU smart enough to not load the three resulting memory lookups into L1-3?

  • The specific RISC-V board that QEMU is emulating makes devices addressable at addresses below 0x80000000; this isn’t part of the RISC-V standard.

    • What does this look like on x86/ARM? Are devices typically memory-mapped in this way?
    • How consistent is this sort of thing across motherboard (?) manufacturers?

  • UART0 is the device that interacts with the console/display

  • Guard pages don’t use up any physical memory because they aren’t marked valid

  • Kernel text pages (instructions) are marked R-X, and kernel data (global variables?) pages are marked RW-

  • This code activates the initial kernel page table:

    void kvminithart() {
  w_satp(MAKE_SATP(kernel_pagetable));
  sfence_vma();
}
    • Once w_satp is done, all addresses are translated via the page table, including the program counter
    • This works because the kernel’s virtual address space is 1:1 mapped with physical memory for the most part
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